Advanced Waveform Models for the Nano-Meter Regime

In the early years of digital system design, it was sufficient to model the delay of elements, so digital simulation tools used step functions to represent signals. As switching speeds increased, it became increasingly necessary to take into account the transition time of the signal. The simplest way of modeling the transition time is to upgrade the signal model from a step to a ramp, and this has been the state of digital design since the early eighties [1, 2]. As speeds increase further, however, the limitation of this approximation have become increasingly apparent. One well known problem is that of threshold selection, which -when not done properlycan lead to to negative delays [3, 4]. Also, many of the deepsubmicron phenomena (e.g. inductive interconnect, coupled noise, and power supply current) are difficult or impossible to model accurately with the ramp model. In this paper, we develop the mathematical basis for a new approach to modeling the waveforms associated with digital circuits. The approach represents a logical extension to current waveform modeling methods and provides a straightforward method to quantify and increase the accuracy of waveform models. 1. PRIOR WORK The simplicity of the ramp approximation of signal waveforms has several advantages: (1) it makes the task of building models for timing analysis easy, (2) it is conceptually easy to grasp and to translate from the model parameters to a pictorial representation or to a Spice input specification, (3) it is information dense in that two real numbers (delay, slope) and a boolean (rising/falling) completely encapsulate the behavior of the waveform in question. Several researchers have recognized the need for more detailed waveform models, [3, 4, 5, 6]. Most, however, attempt to derive the models from a first-principles circuit behavior approach by deriving the waveform model from the analytical solution of the non-linear ordinary differential equation describing the behavior of a simple circuit, such as a CMOS inverter [7]. While such approaches are useful in order to improve our understanding of the behavior of such circuits, they have the following weaknesses: • They are usually restricted to simple output stage topologies for which these analytical techniques can be applied. • They are not related to or integrated into the current timing model characterization methodology. • They do not allow for a tradeoff of complexity vs. accuracy, and do not gracefully degrade to the common ramp model. Time Voltage